Author: Rowan Quni-Gudzinas (QNFO/QWAV) | Date: 2026-06-05 | License: QNFO Unified License Agreement (QNFO-ULA)
1. Introduction
Quantum error correction (QEC) is a co-design problem: the choice of code determines the required qubit connectivity, and the available connectivity constrains which codes are practical. The surface code dominates current hardware roadmaps precisely because its 2D nearest-neighbor connectivity matches the natural layout of superconducting qubits on a chip, trapped ions in a linear chain (with shuttling), and neutral atoms in optical lattices. The marriage of code and hardware has been so successful that it is easy to forget it is a design choice — not a physical necessity.
The metric mismatch hypothesis [Quni-Gudzinas, 2026, “Toward $p$-adic Quantum Error Correction”] challenges the Archimedean assumptions underlying this marriage. If quantum errors are ultrametric rather than Archimedean, then the 2D grid — optimized for Hamming-weight errors with Euclidean locality — may be the wrong hardware topology. An ultrametric error space is isomorphic to a rooted tree, not a flat grid. Correcting errors in such a space with a grid-based code imposes thermodynamic overhead that grows exponentially with hierarchy depth.
This paper proposes the hardware side of the co-design: $p$-adic qubit layouts. These are physical connectivity graphs derived from the Bruhat-Tits tree — the natural geometry of the $p$-adic numbers $\mathbb{Q}_p$ — that are structurally matched to $p$-adic stabilizer codes. In such a layout:
- Qubits are arranged at the leaves of a rooted $p$-ary tree
- Two-qubit gates connect qubits whose $p$-adic distance is small (nearby in the tree)
- Syndrome extraction respects the hierarchy: local checks at each scale feed upward
- Decoding proceeds recursively from leaves to root, mirroring the renormalization group
We develop the theory of these layouts, analyze their physical requirements, and provide concrete implementation sketches for three leading quantum platforms. The layouts are speculative — they depend on the experimental confirmation of ultrametric error structure [Quni-Gudzinas, 2026, “Testing for Ultrametric Error Structure in Quantum Hardware”] — but they provide a concrete target for hardware-software co-design and a testable prediction: if ultrametric errors exist, $p$-adic layouts will outperform grid layouts at scale.
2. The Bruhat-Tits Tree as a Qubit Layout
2.1 Geometry of $\mathbb{Q}_p$
The $p$-adic numbers $\mathbb{Q}_p$ are the completion of $\mathbb{Q}$ under the $p$-adic absolute value $|x|_p = p^{-v_p(x)}$. Their geometry is ultrametric and tree-like. The Bruhat-Tits tree $\mathcal{T}_p$ is the natural geometric object: a regular $(p+1)$-valent infinite tree whose boundary is the projective line $\mathbb{P}^1(\mathbb{Q}_p)$.
Vertices of $\mathcal{T}_p$ correspond to $p$-adic balls (equivalence classes of points with the same $p$-adic valuation). The distance between two boundary points is $p^{-h}$ where $h$ is the height of their lowest common ancestor in the tree. This is an ultrametric distance.
For a finite-depth truncation — corresponding to $p$-adic integers modulo $p^n$, denoted $\mathbb{Z}/p^n\mathbb{Z}$ — we obtain a finite tree of depth $n$ with $p^n$ leaves.
2.2 From Tree to Layout
A $p$-adic qubit layout of depth $n$ consists of:
- Data qubits: $p^n$ qubits placed at the leaves of a depth-$n$ $p$-ary tree.
- Ancilla qubits: placed at internal vertices for syndrome extraction. A vertex at height $h$ (where leaves are $h=0$, root is $h=n$) has access to the $p^h$ leaves in its subtree.
- Connectivity: two-qubit gates are possible between qubits whose tree distance is below a threshold. The natural connectivity graph is the tree itself, with ancilla vertices mediating interactions between data qubits in their subtree.
For $p=2$ (binary tree), the layout requires $2^n$ data qubits and $2^n - 1$ ancilla qubits (one per internal vertex), for a total of $2^{n+1} - 1$ physical qubits.
For $p=3$ (ternary tree), the layout requires $3^n$ data qubits and $(3^n - 1)/2$ ancilla qubits, for a total of $(3^{n+1} - 1)/2$ physical qubits.
2.3 Comparison with 2D Grid
| Property | 2D Grid (Surface Code) | $p$-adic Tree ($p=2$, depth $n$) |
|---|---|---|
| Data qubits | $d^2$ | $2^n$ |
| Connectivity degree | 4 (nearest-neighbor) | $p+1$ at internal vertices, 1 at leaves |
| Max distance between qubits | $\mathcal{O}(d)$ (diameter) | $\mathcal{O}(n) = \mathcal{O}(\log_p \text{#qubits})$ |
| Locality of syndrome checks | Local (nearest neighbors) | Hierarchically local (checks at each scale) |
| Natural code | Surface code | $p$-adic stabilizer code (Phase A) |
| Decoder complexity | $\mathcal{O}(d^3)$ (MWPM) | $\mathcal{O}(n \log n)$ ($p$-adic BP, conjectured) |
The key advantage: the $p$-adic tree has logarithmic diameter. For $2^n = 1024$ data qubits, the grid has diameter $\sim 32$; the tree has diameter $2n = 20$. This difference becomes dramatic at scale: for $10^6$ data qubits, grid diameter $\sim 1000$, tree diameter $\sim 40$.
3. $p$-adic Stabilizer Codes on Tree Layouts
3.1 Code Construction
Recall from Phase A [Quni-Gudzinas, 2026] that a $p$-adic stabilizer code over registers of dimension $p^n$ admits a natural concatenated decomposition:
$$\mathcal{C} = \mathcal{C}0 \succ \mathcal{C}_1 \succ \cdots \succ \mathcal{C}{n-1}$$
where $\mathcal{C}_j$ is a code over registers of dimension $p^{n-j}$.
On the $p$-adic tree layout, this decomposition maps directly to the tree structure:
- Level $j$ of the concatenation corresponds to vertices at height $j$ in the tree
- $\mathcal{C}_j$ uses ancilla qubits at height $j$ for syndrome extraction
- The $p$-adic weight $|P|_p = \max_j \max(|a_j|_p, |b_j|_p)$ measures the “height” of an error in the tree: low-weight errors are “shallow” (near leaves), high-weight errors are “deep” (near root)
3.2 Syndrome Extraction
Syndrome extraction proceeds level-by-level, from leaves to root:
- Level 0 (leaves): Measure local stabilizers coupling adjacent leaves within the same parent. These detect errors affecting individual data qubits.
- Level 1: Ancilla qubits at height 1 measure stabilizers coupling groups of $p$ leaves. These detect errors that are coherent across multiple qubits in the same subtree — exactly the hierarchical errors predicted by the ultrametric noise model.
- Level $j$: Ancilla qubits at height $j$ measure stabilizers coupling entire subtrees of size $p^j$.
This hierarchical extraction is naturally fault-tolerant: errors in syndrome extraction at level $j$ affect only the subtree rooted there and can be corrected by higher-level checks.
3.3 Recursive Decoding
The concatenated structure enables recursive decoding:
- Decode each leaf-level code $\mathcal{C}_0$ independently (base case)
- For $j > 0$: treat each corrected $\mathcal{C}_{j-1}$ block as a single “effective qubit” and decode $\mathcal{C}_j$
This recursive procedure is analogous to renormalization-group decoders for surface codes [Duclos-Cianci & Poulin, 2010] but with the crucial difference that the tree layout provides the hierarchical structure physically, rather than requiring it to be constructed algorithmically.
4. Physical Implementation
4.1 Superconducting Qubits
Connectivity challenge: Superconducting qubits on a 2D chip cannot achieve arbitrary tree connectivity. However, a depth-3 binary tree ($2^3 = 8$ data qubits, 7 ancilla qubits, 15 total) can be embedded on a 2D chip with moderate overhead using the H-tree fractal layout [Ullman, 1984]. The H-tree is a planar embedding of a binary tree that minimizes wire length and is standard in VLSI clock distribution networks.
For larger trees, modular architectures are required: multiple tree modules connected via coupler qubits or tunable buses. IBM’s Nighthawk roadmap [IBM, 2025] with modular chiplet interconnects provides a natural platform.
Gate overhead: Each syndrome extraction round at level $j$ requires $\mathcal{O}(p^j)$ two-qubit gates within the subtree. Across all levels, total gate count per round is $\mathcal{O}(p^n) = \mathcal{O}(N)$, where $N$ is the number of data qubits — matching the surface code’s gate overhead asymptotically.
4.2 Trapped Ions
Trapped ions are a natural fit for $p$-adic layouts. Ion shuttling enables all-to-all connectivity within a trapping zone, and zones can be arranged hierarchically:
- Leaf zones: Contain individual data qubits
- Internal zones: Contain ancilla qubits that interact with all ions in child zones
- Shuttling between zones: Moves ions up and down the tree hierarchy
The Quantinuum H2 processor [Quantinuum, 2025] already demonstrates the necessary shuttling-based connectivity. The key adaptation is the hierarchical arrangement of zones rather than the linear arrangement used for surface codes.
4.3 Neutral Atoms
Neutral atom platforms offer reconfigurable connectivity via optical tweezers. A $p$-adic layout can be implemented by:
- Arranging atoms in a tree pattern in the focal plane
- Using Rydberg blockade for local two-qubit gates at each tree vertex
- Dynamically reconfiguring the arrangement between syndrome extraction levels
QuEra’s 256-atom platform [QuEra, 2025] with Aquila’s reconfigurable geometry is well-suited for proof-of-concept demonstrations at depth $n \leq 3$.
5. Crosstalk and Error Propagation
5.1 Hierarchical Crosstalk
In a tree layout, crosstalk has a natural hierarchical structure:
- Intra-subtree crosstalk: Qubits within the same subtree may experience correlated errors due to shared control lines or spectral crowding. This is “legitimate” in the ultrametric picture — it IS the hierarchical error structure that the code is designed to handle.
- Inter-subtree crosstalk: Qubits in different subtrees are physically separated and should have minimal crosstalk. This maps to the ultrametric property that errors in distant branches should be independent.
This is the opposite of the 2D grid, where crosstalk between ANY neighboring qubits is possible and must be suppressed. The tree layout embraces hierarchical correlation as a feature rather than fighting it as a bug.
5.2 Error Propagation During Gates
A concern for tree layouts: a gate error at an internal vertex affects the entire subtree below it. In the ultrametric picture, such errors are NATURAL — they correspond to the branch errors in the hierarchical noise model of Phase B.
The code distance $d_p$ is defined to protect against precisely these errors. A gate error at height $h$ has $p$-adic weight $p^{-h}$, and the code protects against errors up to a $p$-adic weight threshold. The trade-off between protection and overhead is governed by the $p$-adic quantum bounds (Phase A, §5).
6. Resource Estimates and Scaling
6.1 Qubit Overhead
For a $p$-adic stabilizer code encoding $k$ logical qubits with $p$-adic distance $d_p$, the physical qubit count is:
$$N_{\text{phys}} = \mathcal{O}\left(p^{n} \cdot \frac{p+1}{p}\right)$$
where $n = \lceil \log_p(1/d_p) \rceil$ is the tree depth needed to achieve distance $d_p$.
For comparison with the surface code encoding $k$ logical qubits with distance $d$:
| Code | Physical qubits | Logical error rate scaling | Connectivity |
|---|---|---|---|
| Surface code ($d$) | $\mathcal{O}(d^2)$ | $\sim (p_{\text{phys}}/p_{\text{th}})^{d/2}$ | 2D grid, degree 4 |
| $p$-adic ($d_p$) | $\mathcal{O}(p^{\log_p(1/d_p)})$ | Depends on ultrametric noise model | $p$-ary tree, degree $p+1$ |
The comparison is not straightforward because $d$ and $d_p$ measure different things: Hamming weight vs. $p$-adic weight. Under Archimedean noise, the surface code is optimal. Under ultrametric noise, the $p$-adic code is expected to outperform — but the exact crossover depends on the strength of ultrametric structure, which is precisely what Phase B measures.
6.2 Gate Fidelity Requirements
Tree layouts relax gate fidelity requirements in a specific way:
- Leaf-level gates (between adjacent leaves): Same fidelity requirements as surface code nearest-neighbor gates — must be below threshold.
- Higher-level gates (between ancilla at height $h$ and leaves in its subtree): These gates are used less frequently (once per $\sim p^h$ rounds in a recursive extraction schedule). Their error contribution is diluted by the hierarchy, effectively relaxing their fidelity requirement by a factor of $\sim p^h$.
- Root-level gates: Used only for logical operations and final readout. Their fidelity determines the logical error floor but does not affect the threshold.
This relaxation is a direct consequence of the hierarchical structure and is analogous to the relaxation of long-range gate fidelity in concatenated codes.
7. Prototype Design: $p=2$, Depth 3
We provide a concrete prototype: a depth-3 binary tree layout encoding 8 data qubits with 7 ancilla qubits (15 total physical qubits). This is feasible on current hardware and would serve as a proof-of-concept for $p$-adic QEC.
Layout: 8 data qubits at the leaves of a depth-3 binary tree. 7 ancilla qubits at internal vertices. H-tree embedding on a 2D chip.
Code: A $p$-adic stabilizer code over $\mathbb{Z}/2^3\mathbb{Z} \cong \mathbb{Z}/8\mathbb{Z}$ encoding 1 logical qubit with $p$-adic distance approximately $2^{-2} = 1/4$. This is a small code — not fault-tolerant at scale — but sufficient to demonstrate the hierarchical syndrome extraction and recursive decoding.
Syndrome extraction schedule:
| Level | Qubits involved | Gates per round | Rounds per logical cycle |
|---|---|---|---|
| 0 (leaf pairs) | 2 data + 1 ancilla | 4 CNOTs | Every round |
| 1 (groups of 4) | 4 data + 1 ancilla | 8 CNOTs | Every 2 rounds |
| 2 (root, 8 qubits) | 8 data + 1 ancilla | 16 CNOTs | Every 4 rounds |
Expected performance: If the Phase B protocol detects $\mathcal{U}_2 > 0$ on the target hardware, the 15-qubit $p$-adic prototype should show a logical error rate below the physical error rate — the defining milestone of functional QEC. If $\mathcal{U}_2 \approx 0$, the prototype may underperform a comparable surface code patch, providing a cross-check on the ultrametricity hypothesis.
8. Discussion
8.1 Relationship to Other Hierarchical Architectures
$p$-adic layouts are not the first proposal for hierarchical quantum computing. Related ideas include:
- Concatenated codes with hierarchical syndrome extraction [Knill, 2005]: The idea of recursive decoding is well-established. $p$-adic layouts provide a physical instantiation — the hierarchy is in the hardware, not just the software.
- Fractal codes [Bravyi & Haah, 2013]: These codes have self-similar structure on a 3D lattice. $p$-adic layouts share the fractal motivation but use a different geometry (tree vs. lattice).
- Modular architectures [Monroe et al., 2014]: The idea of connecting small quantum modules into larger systems. $p$-adic layouts specify the topology of the module interconnection (tree, not all-to-all or grid).
8.2 When to Build
The $p$-adic hardware program is conditional on experimental results:
- Wait for Phase B results. If $\mathcal{U}_p \approx 0$ across platforms, $p$-adic layouts offer no advantage and may underperform grid layouts due to connectivity overhead.
- If $\mathcal{U}_p > 0$ is confirmed: The 15-qubit depth-3 prototype (§7) should be the immediate next step. It is feasible on current hardware and would provide the first demonstration of layout-code co-design for ultrametric errors.
- Long-term: If the prototype succeeds and $\mathcal{U}_p$ scales with $d$ as predicted, $p$-adic layouts become a candidate for large-scale fault-tolerant architectures, competing with — and potentially surpassing — 2D grid approaches.
9. Conclusion
We have proposed a family of $p$-adic qubit layouts — tree-structured connectivity graphs derived from the Bruhat-Tits tree — that are structurally matched to $p$-adic stabilizer codes. These layouts exploit the hierarchical structure of ultrametric error spaces rather than fighting it with flat Euclidean grids.
The proposal is speculative: it depends on the experimental confirmation of ultrametric error structure (Phase B). But it completes the logical chain of the $p$-adic QEC program:
- Phase A: Theory — $p$-adic codes have automatic hierarchical structure
- Phase B: Experiment — test whether quantum errors ARE ultrametric
- Phase C (this paper): Hardware — if they are, build chips that match
If the metric mismatch hypothesis is correct, the path to fault-tolerant quantum computing may run through trees, not grids.
Certainty: The Bruhat-Tits tree geometry is [established] mathematics. The mapping to qubit layouts is [speculative]. Physical implementation estimates are [speculative]. Performance comparisons with surface codes are [my conjecture] pending experimental data from Phase B. The entire program is conditional on $\mathcal{U}_p > 0$.